View ICSSSTUAH32868AHLF_3252624.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

datasheet 28-bit configurable registered buffer for ddr2 icssstuah32868a 28-bit configurable registered buffer for ddr2 1 icssstuah32868a 7115/9 description this 28-bit 1:2 configurable registered buffer is designed for 1.7v to 1.9v v dd operation. all inputs are compatible with the jedec standard for sstl_18, except the chip-select gate-enable (csgen), cont rol (c), and reset (reset ) inputs, which are lvcmos. all outputs are edge-controlled circuits optimized for unterminated dimm loads, and meet sstl_18 specifications, except the open-drain error (qerr ) output. the icssstuah32868a operates from a differential clock (clk and clk ). data are registered at the crossing of clk going high and clk going low. the device supports low-power standby operation. when reset is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (vref) inputs are allowed. in addition, when reset is low, all registers are reset and all outputs are forced low except qerr . the lvcmos reset and c inputs must always be held at a valid logic high or low level. to ensure defined outputs from the register before a stable clock has been supplied, reset must be held in the low state during power up. in the ddr2 rdimm application, reset is specified to be completely asynchronous with respect to clk and clk . therefore, no timing relationship can be ensured between the two. when entering reset, the register will be cleared and the data outputs will be driv en low quickly, relative to the time to disable the differential input receivers. however, when coming out of reset, th e register will become active quickly, relative to the time to enable the differential input receivers. as long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of reset until the input receivers are fully enabled, the design of the icssstuah32868a must ensure that the outputs will remain low, thus ensuring no glitches on the output. the icssstuah32868a includes a parity checking function. parity, which arrives one cycle after the data input to which it applies, is checked on the par_in input of the device. the corresponding qerr output signal for the data inputs is generated two clock cycles after the data, to which the qerr signal applies, is registered. the icssstuah32868a accepts a parity bit from the memory controller on the parity bit (par_in) input, compares it with the data received on the dimm-independent d-inputs (d1-d5, d7, d9-d12, d17-d28 when c = 0; or d1-d12, d17-d20, d22, d24-d28 wh en c = 1) and indicates whether a parity error has occurred on the open-drain qerr pin (active low). the convention is even parity, i.e., valid parity is defined as an even number of ones across the dimm-independent data inputs combined with the parity input bit. to calculate parity, all dimm-independent d-inputs must be tied to a known logic state. if an error occurs and the qerr output is driven low, it stays latched low for a minimum of two clock cycles or until reset is driven low. if two or more consecutive parity errors occur, the qerr output is driven low and latched low for a clock duration equal to the parity erro r duration or until reset is driven low. if a parity error occurs on the clock cycle before the device enters the low-power (lpm) and the qerr output is driven low, then it stays lateched low for the lpm duration plus two clock cycles or until reset is driven low. the dimm-dependent signals (dcke0, dcke1, dodt0, dodt1, dcs0 and dcs1 ) are not included in the parity check computation. the c input controls the pinout configuration from register-a configuration (when low) to register-b configuration (when high). the c input should not be switched during normal operation. it should be hardwired to a valid low or high level to configure the register in the desired mode. the device also supports low-power active operation by monitoring both system chip select (dcs0 and dcs1 ) and csgen inputs and will gate the qn outputs from changing states when csgen, dcs0 , and dcs1 inputs are high. if csgen, dcs0 ordcs1 input is low, the qn outputs will function normally. also, if both dcs0 and dcs1 inputs are high, the device will gate the qerr output from changing states. if either dcs0 ordcs1 is low, the qerr output will function normally. the reset input has priority over the dcs0 and dcs1 control and when driven low will force the qn outputs low, and the qerr output high. if the chip-select control functionality is not desired, then the csgen input can be hard-wired to ground, in which case, the setup-ti me requirement for dcs0 and dcs1 would be the same as for the other d data inputs. to control the low-power mode with dcs0 and dcs1 only, then the csgen input should be pulled up to vdd through a pullup resistor. the two v ref pins (a1 and v1) are connected together internally by approximately 150. however, it is necessary to connect only one of the two v ref pins to the external v ref power supply. an unused v ref pin should be terminated with a v ref coupling capacitor.
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 2 icssstuah32868a 7115/9 features ? 28-bit 1:2 registered buffer with parity check functionality ? supports sstl_18 jedec specification on data inputs and outputs ? supports lvcmos switching levels on csgen and reset inputs ? low voltage operation: v dd = 1.7v to 1.9v ? available in 176-ball lfbga package applications ? ddr2 memory modules ? provides complete d dr dimm solution with ics98ulpa877a or idtcspua877a ? ideal for ddr2 400, 533, and 667 block diagram q1a q1b a7 a8 d r ck q d1 ce a2 to 21 other channels (d2-d5, d7, d9-d12, d17-d28) qcs0b k2 l7 qodt0a, qodt1a qodt0b, qodt1b n2, p2 m7, m8 qcke0a, qcke1a qcke0b, qcke1b f2, e2 h8, f8 d r ck q 2 d r ck q d r ck q 2 qcs1a qcs1b l8 j2 d r ck q reset clk dcke0, dcke1 clk dodt0, dodt1 dcs0 csgen dcs1 v ref m2 l1 m1 a5, ab5 d1, c1 n1, p1 k1 l2 j1 2 2 one of 22 channels 2 2 qcs0a
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 3 icssstuah32868a 7115/9 parity logic diagram qcs0a qcs0b k2 l7 qcs1a qcs1b l8 j2 q1a-q5a, q7a, q9a-q12a, q17a-q28a d r ck q ce d r ck q d r ck q reset clk clk par_in dcs0 csgen dcs1 v ref m2 l1 m1 a5, ab5 l3 k1 l2 j1 22 qerr m3 parity generator and error check d r ck q ce 22 22 22 d1-d5, d7, d9-d12, d17-d28 d1-d5, d7, d9-d12, d17-d28 22 d1-d5, d7, d9-d12, d17-d28 d1-d5, d7, d9-d12, d17-d28 22 q1b-q5b, q7b, q9b-q12b, q17b-q28b
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 4 icssstuah32868a 7115/9 block diagram q1a q1b a7 a8 d r ck q d1 ce a2 to 21 other channels (d2-d12, d17-d20, d22, d24-d28) qcs0a qcs0b n2 m7 qodt0a, qodt1a qodt0b, qodt1b k2, j2 l7, l8 qcke0a, qcke1a qcke0b, qcke1b u2, v2 r8, u8 d r ck q 2 d r ck q d r ck q 2 qcs1a qcs1b m8 p2 d r ck q reset clk dcke0, dcke1 clk dodt0, dodt1 dcs0 csgen dcs1 v ref m2 l1 m1 a5, ab5 w1, y1 k1, j1 n1 l2 p1 2 2 2 2 one of 22 channels
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 5 icssstuah32868a 7115/9 parity logic diagram qcs0a qcs0b n2 m7 qcs1a qcs1b m8 p2 q1a-q12a, q17a-q20a, q22a, q24a-q28a d r ck q ce d r ck q d r ck q reset clk clk par_in dcs0 csgen dcs1 v ref m2 l1 m1 a5, ab5 l3 n1 l2 p1 22 qerr m3 parity generator and error check d r ck q ce 22 22 22 22 d1-d12, d17-d20, d22, d24-d28 22 q1b-q12b, q17b-q20b, q22b, q24b-q28b d1-d12, d17-d20, d22, d24-d28 d1-d12, d17-d20, d22, d24-d28 d1-d12, d17-d20, d22, d24-d28
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 6 icssstuah32868a 7115/9 pin configuration 176 ball bga top view a b c d e f g h j k l m n p r t 1234 5 6 7 8 u v w y aa ab
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 7 icssstuah32868a 7115/9 pin configuration 1:2 register a (c = 0) note: nc denotes a no-connect (ball present but not connected to the die). 1:2 register b (c = 1) 6 5 v dd v dd gnd v dd v dd gnd gnd gnd gnd v ref 4 3 2 1 d3 d4 b d5 d6 (dcke1) c q6a (qcke1a) d9 e q8a (qcke0a) d10 f dcs0 k par_in csgen clk l q17a d17 r q19a d18 t qerr reset clk m q15a (qodt0a) d15 (dodt0) n q16a (qodt1a) d16 (dodt1) p q12a d12 h d7 d8 (dcke0) d gnd c d1 d2 a dcs1 j q10a d11 g q21a d19 u d26 d25 aa v ref d28 d27 ab q23a d20 v d22 d21 w d24 d23 y 8 7 q2b q2a q3b q3a q1b q1a qcs0 qcs1 v dd v dd gnd v dd v dd gnd gnd gnd v dd v dd gnd v dd v dd gnd gnd gnd v dd v dd gnd v dd v dd gnd gnd gnd v dd v dd v dd v dd gnd gnd gnd v dd v dd v dd gnd gnd gnd gnd v dd v dd gnd gnd gnd gnd v dd v dd gnd v dd v dd gnd gnd gnd v dd v dd v dd v dd v dd v dd gnd gnd gnd gnd v dd v dd gnd v dd v dd gnd gnd gnd v dd v dd nc q5b q5a q6b (qcke0b) q7a q4b q4a q9a q7b q11a q10b q12b q14b (qcs0b) q8b (qcke0b) q9b q11b q13b (qcs1b) q15b (qodt0b) q16b (qodt1b) q17b q19b q18a q20a q22a q24a q25a q26a q27a q28a q18b q20b q21b q22b q23b q24b q25b q26b q27b q28b 6 5 v dd v dd gnd v dd v dd gnd gnd gnd gnd v ref 4 3 2 1 d3 d4 b d5 d6 c q6a d9 e q8a d10 f k par_in csgen clk l q17a d17 r q19a d18 t m q15a (qcs0a) d15 (dcs0) n q16a (qcs1a) d16 (dcs1) p q12a d12 h d7 d8 d gnd c d1 d2 a d13 (dodt1) j q10a d11 g q21a (qcke0a) d19 u d26 d25 aa v ref d28 d27 ab q23a (qcke1a) d20 v d22 d21 (dcke0) w d24 d23 (dcke1) y 8 7 q2b q2a q3b q3a q1b q1a q13a (qodt1a) v dd v dd gnd v dd v dd gnd gnd gnd v dd v dd gnd v dd v dd gnd gnd gnd v dd v dd gnd v dd v dd gnd gnd gnd v dd v dd v dd v dd gnd gnd gnd v dd v dd v dd gnd gnd gnd gnd v dd v dd gnd gnd gnd gnd v dd v dd gnd v dd v dd gnd gnd gnd v dd v dd v dd v dd v dd v dd gnd gnd gnd gnd v dd v dd gnd v dd v dd gnd gnd gnd v dd v dd nc q5b q5a q6b q7a q4b q4a q9a q7b q11a q10b q12b q14b (qodt0b) q8b q9b q11b q13b (qodt1b) q15b (qcs0b) q16b (qcs1b) q17b q19b q18a q20a q22a q24a q25a q26a q27a q28a q18b q20b q21b (qcke0b) q22b q23b (qcke1b) q24b q25b q26b q27b q28b d14 (dodt0) q14a (qodt0a) qerr reset clk
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 8 icssstuah32868a 7115/9 function table inputs 1 outputs reset dcs0 dcs1 csgen clk clk dx, dodt, dcke qn qcs0 qcs1 qodt, qcke hll x ll hll x hh h l l x l or h l or h x q 0 2 q 0 2 q 0 2 q 0 2 hlhx ll hlhx hh h l h x l or h l or h x q 0 2 q 0 2 q 0 2 q 0 2 hll x ll hll x hh h l l x l or h l or h x q 0 2 q 0 2 q 0 2 q 0 2 hhh l ll hhh l hh h h h l l or h l or h x q 0 2 q 0 2 q 0 2 q 0 2 hhh h lq 0 2 hhh h hq 0 2 h h h h l or h l or h x q 0 2 q 0 2 q 0 2 q 0 2 lx or floating x or floating x or floating x or floating x or floating x or floating l l l l 1 h = high voltage level l = low voltage level x = don?t care = low to high = high to low 2 output level before the indicated steady-state conditions were established.
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 9 icssstuah32868a 7115/9 parity and standby function table inputs 1 outputs reset dcs0 dcs1 clk clk of inputs = h (d1 - d28) par_in 2 qerr 3 hlx even l h hlx odd l l hlx even h l hlx odd h h hxl even l h hxl odd l l hxl even h l hxl odd h h hhh xxqerr 0 4 hxx xxqerr 0 lx or floating x or floating x or floating x or floating x or floating x or floating h 1 h = high voltage level l = low voltage level x = don?t care = low to high = high to low 2 par_in arrives one clock cycle after the data to which it applies. 3 this transition assumes qerr is high at the crossing of clk going high and clk going low. if qerr is low, it stays la tched low for two clock cycles or until reset is driven low. 4 if dcs0 , dcs1 , and csgen are driven high, the device is placed in low-power mode (lpm). if a parity error occurs on the clock cycle before the device enters the lpm and the qerr output is driven low, it stays latched low for the lpm plus two clock cycles or until reset is driven low.
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 10 icssstuah32868a 7115/9 absolute maximum ratings stresses greater than those listed under absolute maximum ratings ma y cause permanen t damage to the device. this is a stress rating only and functional operati on of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended per iods may affect reliability. output buffer characteristics output edge rates over recommended operating free-air temperature range item rating supply voltage, v dd -0.5v to 2.5v input voltage range, v i 1 1 the input and output negative voltage ratings may be exceeded if the ratings of the i/p and o/p clamp current are observed. -0.5v to v dd + 2.5v output voltage range, v o 1,2 2 this current will flow only when the output is in the high state level v o > v ddq . -0.5v to v ddq + 0.5v input clamp current, i ik 50ma output clamp current, i ok 50ma continuous output clamp current, i o 50ma continuous current through each v dd or gnd 100ma package thermal impedance ( ja) 3 3 the package thermal impedance is calculated in accordance with jesd 51. 0m/s airflow 40.4 c/w 1m/s airflow 29.1 c/w storage temperature -65 to +150 c parameter v dd = 1.8v 0.1v units min. max. dv/dt_r 1 4 v/ns dv/dt_f 1 4 v/ns dv/dt_ 1 1 difference between dv/dt_ r (rising edge rate ) and dv/dt_f (falling edge rate). 1v/ns
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 11 icssstuah32868a 7115/9 terminal functions terminal name electrical characteristics description gnd ground input ground v dd 1.8v nominal power supply voltage v ref 0.9v nominal input reference clock clk differential input positive master clock input clk differential input negative master clock input c lvcmos input configuration control inputs - register a or register b reset lvcmos input asynchronous reset input. resets registers and disables vref data and clock differential-input receivers. csgen lvcmos input chip select gate enable ? when high, d1-d28 inputs will be latched only when at least one chip select input is low during the rising edge of the clock. when low, the d1-d28 inputs will be latched and redriven on every rising edge of the clock. d1 - d28 sstl_18 input data input. clocked in on the crossing of the rising edge of clk and the falling edge of clk . dcs0 , dcs1 sstl_18 input chip select inputs ? these pins initiate dram address/command decodes, and as such at least one will be low when a valid address/command is present. the register can be programmed to redrive all d inputs (csgen high) on ly when at least one chip select input is low. if csgen, dcs0 , and dcs1 inputs are high, d1-d28 inputs will be disabled. dcke0, dcke1 sstl_18 input the outputs of this register bit will not be suspended by the dcs0 and dcs1 controls dodt0, dodt1 sstl_18 input the outputs of this register bit will not be suspended by the dcs0 and dcs1 controls par_in sstl_18 input parity input arrives one cycle after corresponding data input q1 - q28 1.8v cmos data outputs that are suspended by the dcs0 and dcs1 controls qcs0 , qcs1 1.8v cmos data output that will not be suspended by the dcs0 and dcs1 controls qcke0, qcke1 1.8v cmos data output that will not be suspended by the dcs0 and dcs1 controls qodt0, qodt1 1.8v cmos data output that will not be suspended by the dcs0 and dcs1 controls qerr open drain output output error bit, generated one cycle after the corresponding data output nc no connection
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 12 icssstuah32868a 7115/9 operating characteristics, t a = 25 c the reset and cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. the differential inputs must not be floating unless reset is low. symbol parameter min. typ. max. units v dd i/o supply voltage 1.7 1.8 1.9 v v ref reference voltage 0.49 * v dd 0.5 * v dd 0.51 * v dd v v tt termination voltage v ref - 0.04 v ref v ref + 0.04 v v i input voltage 0 v dd v v ih ac high-level input voltage data csr and pa r _ i n inputs v ref + 0.25 v v il ac low-level input voltage v ref - 0.25 v ih dc high-level input voltage v ref + 0.125 v il dc low-level input voltage v ref - 0.125 v ih high-level input voltage reset , c0, c1 0.65 * v ddq v v il low-level input voltage 0.35 * v ddq v icr common mode input range clk, clk 0.675 1.125 v v id differential input voltage 600 mv i oh high-level output current -12 ma i ol low-level output current 12 t a operating free-air temperature 0 +70 c
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 13 icssstuah32868a 7115/9 dc electrical characterist ics over operating range following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, v ddq /v dd = 2.5v 0.2v. symbol parameter test conditions min. typ. max. units v oh output high voltage i oh = -12ma, v ddq = 1.7v 1.2 v v ol output low voltage i ol = 12ma, v ddq = 1.7v 0.5 v i il all inputs v i = v dd or gnd; v dd = 1.9v -5 +5 a i dd static standby i o = 0, v dd = 1.9v, reset = gnd 200 a static operating i o = 0, v dd = 1.9v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk = clk = v ih ( ac ) or v il ( ac ) 10 ma i o = 0, v dd = 1.9v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk = v ih ( ac ), clk = v il ( ac ) 170 i ddd dynamic operating (clock only) i o = 0, v dd = 1.8v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk and clk switching 50% duty cycle 500 a/clock mhz dynamic operating (per each data input) 1:2 mode i o = 0, v dd = 1.8v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk and clk switching 50% duty cycle. one data input switching at half clock frequency, 50% duty cycle. 82 a/clock mhz/ data c i data inputs v i = v ref 250mv 2 3.5 pf clk and clk v icr = 0.9v, v ipp = 600mv 3 4 reset v i = v dd or gnd 5
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 14 icssstuah32868a 7115/9 timing requirements over recommend ed operating free-air temperature range switching characteristics over recommended free air operating range (unless otherwise noted) symbol parameter v dd = 1.8v 0.1v units min. max. f clock clock frequency 410 mhz t w pulse duration, clk, clk high or low 1 ns t act 1,2 1 this parameter is not production tested. 2 v ref must be held at a valid input voltage level and data inputs must be held at valid voltage levels for a minimum time of t act (max) after reset is taken high. differential inputs active time 10 ns t inact 1,3 3 v ref data and clock inputs must be held at valid input voltage levels (not floating) for a minimum time of t inact (max) after reset is taken low. differential inputs inactive time 15 ns t su setup time dcs0 before clk , clk , dcs1 and csgen high; dcs1 before clk , clk , dcs0 and csgen high; 0.7 ns dcs0 before clk , clk , dcs1 low and csgen high or low; dcs1 before clk , clk , dcs0 low and csgen high or low 0.5 ns dodtn, dcken, par_in, and data before clk , clk 0.5 ns t h hold time dcsn , dodt,n dcken, and data after clk , clk 0.5 ns par_in after clk , clk 0.5 ns symbol parameter v dd = 1.8v 0.1v units min. max. f max max input clock frequency 410 mhz t pdm propagation delay, single bit switching, clk / clk to qn 1.3 1.9 ns t pdmss propagation delay, simultaneous switching, clk / clk to qn 2 ns t lh low to high propagation delay, clk / clk to qerr 1.2 3 ns t hl high to low propagation delay, clk / clk to qerr 0.8 2.4 ns t plh high to low propagation delay, reset to qn 3.2 ns t phl low to high propagation delay, reset to qerr 3.5 ns
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 15 icssstuah32868a 7115/9 register timing notes: 1.after reset is switched from low to high, all data and par_in inputs signals must be set and held low for a minimum time of t actmax , to avoid false error. 2.if the data is clocked in on the n clock pulse, the qerr output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. n n+1 n+2 n+3 n+4 t pdm, t pdmss clk to q t su clk clk dn, dodtn, dcken parin qerr qn, qodtn, qcken t phl t su t h t act t h data to qerr latency clk to qerr clk to qerr t phl, t plh dcs1 dcs0 csgen reset h, l, or x h or l
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 16 icssstuah32868a 7115/9 register timing note: 1.if the data is clocked in on the n clock pulse, the qerr output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock puls e. if an error occurs and the qerr output is driven low, it stays latched low for a minimum of two clock cycles or until reset is driven low.
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 17 icssstuah32868a 7115/9 register timing note: 1.after reset is switched from low to high, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of t inactmax . clk clk dn, dodtn, dcken parin qerr qn, qodtn, qcken dcs1 dcs0 csgen reset h, l, or x h or l t inact t rphl reset to q t rplh reset to qerr
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 18 icssstuah32868a 7115/9 test circuits and waveforms (v dd = 1.8v 0.1v) simulation load circuit voltage and current waveforms inputs active and inactive times voltage waveforms - pulse duration voltage waveforms - setup and hold times production-test load circuit voltage waveforms - propagation delay times voltage waveforms - propagation delay times notes: 1. c l includes probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and io = 0ma 3. all input pulses are supplied by generators having the following characteristics: prr 10mhz, zo = 50 , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v tt = v ref = v dd /2 6. v ih = v ref + 250mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. 7. v il = v ref - 250mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. v id = 600mv. 9. t plh and t phl are the same as t pdm . c l =30pf r l =1k dut out r l= 100 clk inputs t l =50 t l =350ps,50 test point clk clk v dd r l =1k test point test point v dd 0v v dd /2 lvcmos reset input i dd v dd /2 t inact t act 10% 90% v icr v id v icr input t w v ref v ih v il v ref input v icr v id t su t h clk clk z o =50 test point r l =50 dut out clk inputs clk v dd /2 clk z o =50 z o =50 test point test point clk v icr v id t plh t phl output v oh v ol v icr v tt v tt clk v oh v ol v ih v il t rphl v dd /2 v tt lvcmos reset input output
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 19 icssstuah32868a 7115/9 test circuits and waveforms (v dd = 1.8v 0.1v) load circuit: high-to-l ow slew-rate adjustment voltage waveforms: high-to-low slew-rate adjustment load circuit: low-to-h igh slew-rate adjustment voltage waveforms: low-to-h igh slew-rate adjustment load circuit: error output measurements voltage waveforms: open drain output low-to-high transition time (w ith respect to reset input) voltage waveforms: open drain output high-to-low transition time (with r espect to clock inputs) voltage waveforms: open drain output low-to-high transition time (with r espect to clock inputs) notes: 1. cl includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: prr 10mhz, zo = 50 , input slew rate = 1 v/ns 20% (unless otherwise specified). c l =10pf r l =50 dut out test point v dd v oh 80% 20% v ol output dv_f dt_f c l =10pf r l =50 dut out test point v ol 20% 80% v oh output dv_r dt_r c l =10pf r l =1k dut out test point v dd v oh v cc output waveform 2 lvcmos reset input t plh v cc /2 0.15v 0v 0v v cc v icr t hl timing inputs v icr v i(pp) output waveform 1 v cc /2 v ol v oh output waveform 2 0.15v 0v v icr t hl timing inputs v icr v i(pp)
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 20 icssstuah32868a 7115/9 package outline and pack age dimensions - bga package dimensions are kept current with jedec publication no. 95 seating plane 0.12 c c a b c d a1 d e top view t htyp dtyp 4321 numeric designations for horizontal grid bref cref typ -e- typ -e- d1 e1 alpha designations for vertical grid (letters i, o, q, and s not used) all dimensions in millimeters d 15.00 bsc e 6.00 bsc t min/max 0.94/1.20 e 0.65 bsc d min/max 0.35/0.45 h min/max 0.25/0.35 d1 13.65 bsc e1 4.55 bsc b 0.675 c 0.725 ball grid ref. dims note: ball grid total indicates maximum ball count for package. lesser quantity may be used. * source ref.: jedec publication 95, mo-205*, mo-255**, mo-246*** 10-0055 horiz 8 vert 22 total 176 ***
icssstuah32868a 28-bit configurable register ed buffer for ddr2 commercial temperature grade 28-bit configurable registered buffer for ddr2 21 icssstuah32868a 7115/9 ordering information xxx xx package device type hlf low profile, fine pitch, ball grid array - lead-free 28-bit configurable registered buffer for ddr2 868a 32 double density icssstuah xx family shipping carrier x t tape and reel
? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 innovate with idt and accelerate your future netw orks. contact: www.idt.com icssstuah32868a 28-bit configurable registered buffe r for ddr2 commercial temperature grade

▲Up To Search▲

Price & Availability of ICSSSTUAH32868AHLF

	To Download ICSSSTUAH32868AHLF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .